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AC Performance Guaranteed over Temperature? High Power Supply Noise Immunity? Isolation of High Speed Logic Systems? Computer-Peripheral Interfaces?
Switching Power Supplies? Isolated Bus Driver Networking Applications? Ground Loop Elimination? This combination results in very high data rate capability and low input current.
F bypass capacitor must be connected between pins 5 and 8. The hysteresis provides differential mode noise immunity and minimizes the potential for output signal chatter. Typical data rates are 40 MBd.
Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must ben ensured by protective circuits in application. See Note Notes: 1. Each channel. Duration of output short circuit time not to exceed 10 ms.
Device considered a two terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together. The typical data shown is indicative of what can be expected using the application circuit in Figure This specification simulates the worst case operating conditions of the HCPL over the recommended operating temperature and VCC range with the suggested application circuit of Figure Propagation delay skew is discussed later in this data sheet.
Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the VCC line that the device will withstand and still remain in the desired logic state. Use of a 0. F bypass capacitor connected between pins 8 and 5 adjacent to the device is required. Typical Logic Low Output Voltage vs. Logic Low Output Current. Figure 2. Typical Logic High Output Voltage vs.
Logic High Output Current. Figure 3. Typical Output Voltage vs. Input Forward Current. Figure 4. Figure 5. Figure 6. Typical Propagation Delay vs. Ambient Temperature. Figure 7. Figure 8. Typical Pulse Width Distortion vs. Figure Typical Enable Propagation Delay vs.
Parallel Data Transmission Example. Modulation Code Selections. The propagation delay from low to high tPLH is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low tPHL is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low see Figure 5.
PWD can be expressed in percent by dividing the PWD in ns by the minimum pulse width in ns being transmitted. Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern.
If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions i.
As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 16 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signals are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast.
Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 16 shows that there will be uncertainty in both the data and the clock lines.
It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived.
From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPHZ. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem.
This circuit utilizes several techniques to minimize the total pulse-width distortion at the output of the optocoupler. By using two inverting TTL gates connected in series, the inherent pulse-width distortion of each gate cancels the distortion of the other gate.
For best results, the two seriesconnected gates should be from the same package. The circuit in Figure 13 also uses techniques known as prebias and peaking to enhance the performance of the optocoupler LED. This small prebias voltage partially charges the junction capacitance of the LED, allowing the LED to turn on more quickly. The speed of the LED is further increased by applying 14 momentary current peaks to the LED during the turn-on and turnoff transitions of the drive current.
These peak currents help to charge and discharge the capacitances of the LED more quickly, shortening the time required for the LED to turn on and off. The typical and worst-case switching parameters given in the data sheet can be met using common 74LS TTL inverting gates or buffers.
Use of faster TTL families will slightly reduce the overall propagation delays from the input of the drive circuit to the output of the optocoupler, but will not necessarily result in lower pulse-width distortion or propagation delay skew. This reduction in overall propagation delay is due to shorter delays in the drive circuit, not to changes in the propagation delays of the optocoupler; optocoupler propagation delays are not affected by the speed of the logic used in the drive circuit.
HCPL-2400 View Datasheet(PDF) - HP => Agilent Technologies